Using Default Values for Variables

You can define a default value for a node or group that is used when the value of the node or group is not specified elsewhere in the file. AHDL also allows you to assign the value of a node or group more than once in a single file. If these multiple assignments conflict, the default value is used to resolve the conflict. When no defaults are specified, the default value is GND.

You can use the AHDL Defaults Statement to specify default values for variables used in Truth Table, If Then, and Case Statements. For example, since the Logic Synthesizer automatically connects all AHDL truth table outputs to GND when no truth table input conditions are satisfied, you can use one or more Defaults Statements to drive truth table outputs to VCC instead.

NOTE You should not confuse default values for variables with default values for ports that are assigned in the Subdesign Section.

The default1.tdf file shown below evaluates inputs and chooses one of five ASCII codes based on the inputs.

SUBDESIGN default1
   i[3..0]          : INPUT;
   ascii_code[7..0] : OUTPUT;
      ascii_code[] = B"00111111"; % ASCII question mark "?" %

      i[3..0] => ascii_code[];

      B"1000" => B"01100001"; % "a" %
      B"0100" => B"01100010"; % "b" %
      B"0010" => B"01100011"; % "c" %
      B"0001" => B"01100100"; % "d" %

When an input pattern matches one of the patterns shown on the left of the Truth Table Statement, the table's outputs are set to the corresponding pattern on the right. If the input pattern does not match any pattern on the left, the outputs default to B"00111111", that is, nodes ascii_code[5..0] are driven to VCC while nodes ascii_code[7..6] are connected to GND.

The default2.tdf file shown below illustrates how conflicts arise when a single node is assigned more than one value, and how these conflicts are resolved by AHDL.

SUBDESIGN default2
   a, b, c                      : INPUT;
   select_a, select_b, select_c : INPUT;
   wire_or, wire_and            : OUTPUT;
      wire_or = GND;
      wire_and = VCC;

   IF select_a THEN
      wire_or = a;
      wire_and = a;
   END IF;

   IF select_b THEN
      wire_or = b;
      wire_and = b;
   END IF;

   IF select_c THEN
      wire_or = c;
      wire_and = c;
   END IF;

In this example, wire_or is set to the values of a, b, or c, depending on the values of the select_a, select_b, and select_c signals. If none of these signals is VCC, wire_or defaults to GND.

If more than one of the select_a, select_b, or select_c signals are VCC, wire_or is set to the logical OR of the corresponding input values. For example, if select_a and select_b are VCC, wire_or is set to the logical OR of a and b.

The wire_and signal works in the same way, except that it defaults to VCC when none of the "select" signals is VCC, and is set to the logical AND of the corresponding input values when more than one of the signals is VCC.

NOTE Go to Node Declaration for information on how AHDL resolves conflicts when a node is assigned more than one value.

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