Implementing Active-Low Logic

An active-low signal becomes active when its value is GND. Active-low signals can be useful for controlling memory, peripheral, and microprocessor chips.

The daisy.tdf file shown below is a module of a daisy-chain arbitration circuit. This module makes requests for bus access to the preceding module in the daisy chain. It receives requests for bus access from itself and from the next module in the chain. Bus access is granted to the highest-priority module that requests it.

   /local_request   : INPUT;
   /local_grant     : OUTPUT;
   /request_in      : INPUT;    % from lower priority  %
   /request_out     : OUTPUT;   % to higher priority   %
   /grant_in        : INPUT;    % from higher priority %
   /grant_out       : OUTPUT;   % to lower priority    %
       /local_grant   = VCC;    % active-low output         %
       /request_out   = VCC;    % signals should default    %
       /grant_out     = VCC;    % to VCC                    %

IF /request_in == GND # /local_request == GND THEN
      /request_out = GND;
   END IF;

   IF /grant_in == GND THEN
      IF /local_request == GND THEN
         /local_grant = GND;
      ELSIF /request_in == GND THEN
         /grant_out = GND;
      END IF;
   END IF;

All signals in this file are active low. Altera® recommends that you choose a node-naming scheme that clearly indicates active-low signal names — such as, an initial "n" or a slash (/) — and use it consistently. A slash is not an operator, but is simply part of the signal name.

If Then Statements are used to determine whether modules are active, that is, whether the signal equals GND. If a signal is active, the equations following the appropriate If Then Statement are activated. The Defaults Statement specifies that a signal is assigned to VCC when it is not active.

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