Variable Section

The optional Variable Section is used to declare and/or generate any variables used in the Logic Section. AHDL variables are similar to variables in a high-level programming language; they are used to define buried (internal) logic.

The following example shows a Variable Section:

	a, b, c	[WIDTHAD-1..0]	: NODE;
	ts_node			: TRI_STATE_NODE;
	temp 			: DFFE;

		20kcounter	: lpm_counter WITH (LPM_WIDTH=WITHAD-1);
NOTE This example uses the predefined Altera® parameter DEVICE_FAMILY, which represents the current device family that you specified for compilation with the Device page of the Settings dialog box (Assignments menu).

The Variable Section can include the following statements or constructs:

NOTE The Variable Section can also contain If Generate Statements which can be used to generate Instance, Node, Register, and State Machine Declarations.


The Variable Section has the following characteristics:

NOTE Compiler-generated names that contain the tilde (~) character may appear in the compilation database for a project. If you back-annotate the assignments in the database, these names will then appear in the project's Compiler Settings File (.csf). The tilde character is reserved for Compiler-generated names only; you cannot use it in your own pin, node, and group names.

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