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Consider the following guidelines when working with Text Design Files (.tdf), VHDL Design Files (.vhd), and Verilog Design Files (.v):

• Use white space (blank lines, spaces, and tabs) around logical groups.

• Do not place extra spaces before semicolons (;) commas (,), closing double quotation marks ("), or closing parentheses ()), or after opening double quotation marks (") or opening parentheses (().

  Unformatted:	Formatted:
  DFF ( d , clk , clrn , prn );	DFF (d, clk, clrn, prn);

  
  

• Use tabs and spaces to align colons, truth table entries, identifiers, and so forth.

  Unformatted:	Formatted:
  in1, clk : INPUT; out1, out2, out3 : OUTPUT; bus[8..1] : BIDIR input clr, ql; reg q2;	in1, clk : INPUT; out1, out2, out3 : OUTPUT; bus[8..1] : BIDIR input clr, ql; reg q2

  
  

• Leave a blank space before an opening parenthesis to separate it from a keyword or identifier.

  Unformatted:	Formatted:
  OF BITS(q[3..0]) module maxpld(clk, d, e); if(state)	OF BITS (q[3..0]) module maxpld (clk, d, e); if (state)

  
  

• Place one blank space before and after operators and comparators (unless you are aligning signal names or identifiers).

  Unformatted:	Formatted:
  enable = !a3&a2&a1&a0; enable = (a[]==B"0111");	enable = !a3 & a2 & a1 & a0; enable = (a[] == B"0111");

  
  

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