An ASCII text file (with the extension .v or .verilog) created with the Quartus^® II Text Editor or any other standard text editor. As Verilog Design File contains design logic that is defined with Verilog HDL.

A Verilog Design File can contain any combination of the Verilog HDL constructs supported by the Quartus II software. For more information, see "Quartus II Verilog HDL Support."

You can easily incorporate primitives, Altera-provided and user-defined megafunctions, and user-defined macrofunctions into a Verilog Design File. You can use a Module Instantiation to call primitives and other Altera-provided logic functions. To define and use a logic function, you can generate an AHDL Include File (.inc) for the logic function and then use a Module Instantiation to insert an instance of the logic function. This method can also be used to incorporate Verilog HDL logic into another Verilog Design File. Some Altera-provided primitives can also be expressed as logical operators in Boolean expressions or as Verilog HDL gate primitives.

A single Verilog Design File can be used to define all logic in a project, or can be incorporated at any hierarchy level in a hierarchical project. In the Text Editor, you can create a Block Symbol File (.bsf) or an AHDL Include File (.inc) that represents a Verilog Design File with the Create/Update > Create Symbol Files for Current File and Create/Update > Create AHDL Include Files for Current File commands (File menu), respectively. You can incorporate a BSF into a Block Design File (.bdf), and an AHDL Include File into an AHDL Text Design File (.tdf) or another Verilog Design File.

The Quartus II Compiler can also create Verilog Output Files (.vo) for use with other EDA tools.

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