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Starts a VHDL-style comment, which extends to the end of the line. (See Comments & Documentation for more information.)

• Enclose and define sequential group names.

• Enclose port names in Subdesign Sections and Function Prototype Statements.

• Optionally enclose inputs and outputs of truth tables in Truth Table Statements.

• Enclose bits and states of State Machine Declarations.

• Enclose highest priority operations in Boolean and arithmetic expressions.

• Enclose parameter definitions in Parameters Statements, Instance Declarations, and parameter names in Function Prototype Statements and in-line logic function references.

• Optionally enclose the condition in an Assert Statement.

• Enclose the arguments of evaluated functions in Define Statements.

• Enclose the range of a single-range or dual-range group name.

• Enclose a number in the name of a node that is part of a single-range or dual-range group.

• Enclose a range in the name of a set of nodes that are part of a single-range or dual-range group.

• Enclose strings in Title Statements, Parameters Statements, and Assert Statements.

• Enclose a file name in Include Statements.

• Enclose digits in non-decimal numbers.

• Separates symbolic names of logic function variables from port names.

• Separates extensions from file names.

• Assigns default GND and VCC values to inputs in a Subdesign Section.

• Assigns settings to options in an Options Statement.

• Assigns a default value to a parameter in a Parameters Statement or an in-line logic function reference.

• Assigns values to state machine states.

• Assigns values in Boolean equations.

• Connects a signal to a port in an in-line logic function reference that uses named port association.

• Separates inputs from outputs in Truth Table Statements.

• Separates WHEN clauses from Boolean expressions in Case Statements.

- Altera -