var_div

This is a local mirror of the Altera FreeCore Library. It is no longer supported.

FreeCore Function #16:
Variable Frequency Divider
Module name: var_div
Current release: version 1.0, January 30, 1998
Contributed by: Rune Baeverrud

Description

This function is similar to the div_by_n function also found in the FreeCore Library. Please read the div_by_n documentation for a description. The difference is that while div_by_n divides a frequency by a fixed value provided as a parameter, var_div will divide a frequency by a variable value provided at it's D[] input. The parameter value WIDTH determines the width of the D[] and Q[] ports.

NOTE:
The var_div divider value provided at the D[] input is actually the maximum value of the internal counter. So - if you specify a value of 6, the counter will cycle through 0..6 which makes this a divide by 7 effectively. This is not the case with the div_by_n module, where a DIVISOR of 6 provides a divide by 6 effectively.

NOTE:
When you change the value at the D[] input, for instance from 4 to 2, and the counter value currently is at 3, the counter will continue cycling through the complete range of possible values, limited by the width of the counter. You should therefore consider using sclr each time you change the D[] input value to make sure the counter is reset to zero.

Shown below is a simple schematic using the var_div module, and it also demonstrates the cascadability of the module:

...and this is how the simulator output of the above schematic looks like:

Ports & Parameters Description

PARAMETERS

WIDTH Width of D[] and Q[] ports and internal counter, and determines the maximum divisor value. For instance, with a WIDTH value of 8, the D[] input will be 8 bits carrying any number from 0 to 255.

INPUT PORTS

SysClk System clock input.

cnt_en The internal counter counts on the positive edge of SysClk whenever cnt_en is high. Default value is VCC.

sclr The internal counter is cleared on the positive edge of SysClk whenever sclr is high, regardless of the state of cnt_en. If both cnt_en and sclr is asserted, sclr will take precedence. Default value is GND.

D[] Divider value.

OUTPUT PORTS

Every_n (SysClk AND Enable) divided by (D[] + 1), delayed by 1 SysClk cycle.

Q[] Current internal counter value. For instance - with a DIVISOR value of 7, the counter will cycle through values 0..6 whic can be read at the Q[] output.

Last updated 08 Feb 2001 11:53

PARAMETERS
WIDTH	Width of D[] and Q[] ports and internal counter, and determines the maximum divisor value. For instance, with a WIDTH value of 8, the D[] input will be 8 bits carrying any number from 0 to 255.
INPUT PORTS
SysClk	System clock input.
cnt_en	The internal counter counts on the positive edge of SysClk whenever cnt_en is high. Default value is VCC.
sclr	The internal counter is cleared on the positive edge of SysClk whenever sclr is high, regardless of the state of cnt_en. If both cnt_en and sclr is asserted, sclr will take precedence. Default value is GND.
D[]	Divider value.
OUTPUT PORTS
Every_n	(SysClk AND Enable) divided by (D[] + 1), delayed by 1 SysClk cycle.
Q[]	Current internal counter value. For instance - with a DIVISOR value of 7, the counter will cycle through values 0..6 whic can be read at the Q[] output.