cuart_tx

This is a local mirror of the Altera FreeCore Library. It is no longer supported.

FreeCore Function #2:
Compact UART, Transmitter Module
Module name: cuart_tx
Current release: version 1.0, April 4, 1997
Contributed by: Rune Baeverrud

The Compact UART will give you UART (Universal Asynchronous Receiver Transmitter) functionality with a minimum of space requirements. The Compact UART is fully LPM parameterizable and will never waste space on unused functionality. With the Compart UART, you may build UARTs of any word length. How about a 49-bit UART with 7 stop bits? With Compact UART, that is your decision.

Shown below is a sample schematic using the cuart_tx module:

The transmitter module is here combined with the div_by_n module, also found in the FreeCore Library. Data is sent out with a speed of 66MHz/6875 = 9600bps. A possible bottleneck here is the divider function, which contains a counter large enough to accomodate a count value of 6875. A solution to this bottleneck problem is to cascade several smaller div_by_n modules.

Module Description

Interfacing to cuart_tx is very straight-forward, and the description of the pins and parameters are given below. A reference design using the transmitter and receiver module, and combining them with a microprocessor interface, is also available in the FreeCore Library.

PARAMETERS

MSB_FIRST Determines if data is sent with most significant bit first or least significant bit first. Default value is "YES".

STOP_BITS Number of stop bits to send trailing each data word.

WIDTH Data Width. The data width may be any number equal to or larger than 2.

INPUT PORTS

SysClk System clock input.

BaudGen Baud rate generator input. Data will be sent in the same rate as BaudGen.

Load Loads a new data word from Din[] into the Transmitter Module and starts transmitting. If a transmission is in progress, the Load input will be ignored.

D[] Parallel data input.

OUTPUT PORTS

TxD Serial data output.

TxBusy If 1, a transmission is pending, and Load will be ignored until transmission is complete and TxBusy returns to 0.

Last updated 08 Feb 2001 12:28

PARAMETERS
MSB_FIRST	Determines if data is sent with most significant bit first or least significant bit first. Default value is "YES".
STOP_BITS	Number of stop bits to send trailing each data word.
WIDTH	Data Width. The data width may be any number equal to or larger than 2.
INPUT PORTS
SysClk	System clock input.
BaudGen	Baud rate generator input. Data will be sent in the same rate as BaudGen.
Load	Loads a new data word from Din[] into the Transmitter Module and starts transmitting. If a transmission is in progress, the Load input will be ignored.
D[]	Parallel data input.
OUTPUT PORTS
TxD	Serial data output.
TxBusy	If 1, a transmission is pending, and Load will be ignored until transmission is complete and TxBusy returns to 0.