cuart_rx

This is a local mirror of the Altera FreeCore Library. It is no longer supported.

FreeCore Function #3:
Compact UART, Receiver Module
Module name: cuart_rx
Current release: version 1.0, April 4, 1997
Contributed by: Rune Baeverrud

The Compact UART will give you UART (Universal Asynchronous Receiver Transmitter) functionality with a minimum of space requirements. The Compact UART is fully LPM parameterizable and will never waste space on unused functionality. With the Compart UART, you may build UARTs of any word length. How about a 49-bit UART with 7 stop bits? With Compact UART, that is your decision.

Shown below is a sample schematic using the cuart_rx module:

The receiver module is here combined with the div_by_n module, also found in the FreeCore Library. Data is sent out with a speed of 66MHz/859/8 = 9600bps. For lower data speeds, I recommend using several cascaded div_by_n modules to avoid high counter values, which is a possible bottleneck.

Module Description

Interfacing to cuart_rx is very straight-forward, and the description of the pins and parameters are given below. A reference design using the transmitter and receiver module, and combining them with a microprocessor interface, is also available in the FreeCore Library.

PARAMETERS

MSB_FIRST Determines whether MSB or LSB in the data stream is expected first. Default is "YES", indicating that MSB is expected first.

RX_BUFFER May be "YES" or "NO". If the parameter value is set to "YES", the Receiver Module will be double-buffered. A value of "YES" will also consume more logic cells. Default value is "NO".

WIDTH Data Width. The data width may be any number equal to or larger than 2.

INPUT PORTS

SysClk System clock input.

BaudGen Baud rate generator input. Required to be 8 times the actual data rate.

RxD Serial data input.

OUTPUT PORTS

D[] Parallel data output.

Sample Goes to 1 for one system clock cycle each time RxD is sampled.

DValid If 1, it indicates that a valid data value (last data word received) is present on the Dout[] output. DValid goes to 1 at the same time as data is presented on the D[] output, and goes to 0 one clock period before D[] is changed.

DEnable Goes to 1 for one system clock cycle each time valid data is presented on the D[] output.

Last updated 08 Feb 2001 12:29

PARAMETERS
MSB_FIRST	Determines whether MSB or LSB in the data stream is expected first. Default is "YES", indicating that MSB is expected first.
RX_BUFFER	May be "YES" or "NO". If the parameter value is set to "YES", the Receiver Module will be double-buffered. A value of "YES" will also consume more logic cells. Default value is "NO".
WIDTH	Data Width. The data width may be any number equal to or larger than 2.
INPUT PORTS
SysClk	System clock input.
BaudGen	Baud rate generator input. Required to be 8 times the actual data rate.
RxD	Serial data input.
OUTPUT PORTS
D[]	Parallel data output.
Sample	Goes to 1 for one system clock cycle each time RxD is sampled.
DValid	If 1, it indicates that a valid data value (last data word received) is present on the Dout[] output. DValid goes to 1 at the same time as data is presented on the D[] output, and goes to 0 one clock period before D[] is changed.
DEnable	Goes to 1 for one system clock cycle each time valid data is presented on the D[] output.